A conventional multilayer capacitor disclosed in, for example, Patent Literature 1 (Japanese Unexamined Patent Publication No. H7-135124) is known. The multilayer capacitor disclosed in Patent Literature 1 is a multilayered ceramic capacitor in which a plurality of dielectric layers, on surfaces of which electrode patterns are arranged, are laminated, in which a plurality of parallel connected capacitor components are formed therein, and in which some of the electrode patterns arranged on the ceramic dielectric layers are divided into a plurality of sections such that each of the parallel connected capacitor components is configured to connect at least two capacitor components in series.